With rapid development of mobile communication technologies, people have an increasingly-urgent requirement for high performance, high speed, and low delay of a communication system, and therefore raise an increasingly-higher requirement for a processor of an electronic device. The processor of an electronic device has developed from single-core to multiple-core and then to many-core. A many-core processor uses a non-cache-coherent architecture and a multi-kernel operating system (multi-kernel OS). Various processes of a many-core processor communicate with each other by means of message transmission.
In the prior art, inter-core communication is implemented by a shared memory, polling, and Inter-Process Interrupt (IPI) on a non-cache-coherent many-core processor platform. A shared memory is split into multiple blocks that have a same size as a cache line. A transmit end places a message body into the shared memory, places a channel identifier (channel ID) that includes memory address information into a Message Passing Buffer (MPB), and instructs a receive end through the IPI to obtain the channel ID from the MPB. Finally, a user-layer application at the receive end reads the message body from the shared memory.
In the process of implementing the foregoing inter-core communication, the inventor has discovered that the prior art at least has the following problem. The user-layer application needs to read the message body from the shared memory, thereby decreasing the speed of reading the message body and degrading user experience.